Traditionally, C4 (Controlled Collapse Chip Connection) bumps have been used to bond a chip to a chip carrier (substrate). Conventionally, the C4 bumps (solder bumps) are made from lead tin solder. For example, lead is known to mitigate coefficient or thermal expansion (CTE) mismatch between the package and the substrate (i.e., organic laminate). For organic substrates, the solder commonly is made from eutectic lead tin. Accordingly, stresses imposed during the cooling cycle are mitigated by the C4 bumps, thus preventing delaminations or other damage from occurring to the chip or the substrate.
However, lead-free requirements are now being imposed by many countries forcing manufacturers to implement new ways to produce chip to substrate joints. For example, solder interconnects consisting of tin/copper, tin/silver and SAC alloys have been used as a replacement for leaded solder interconnents. However, the higher melting points and stiffness of such lead free solders vs. eutectic leaded solders causes a transfer of stress through the C4 joint during assembly process (e.g., during a cooling cycle after reflow). Cracks in chip metallurgy under C4 bumps have been observed, which are named “white bumps” due to their appearance in sonoscan type inspection process.
More specifically, in practice, the organic laminate has a CTE of about 18 to 20; whereas, the CTE of the chip is about 3. During the soldering process, e.g., reflow oven, the temperatures can range from about 250° C. to 260° C. This high temperature expands the organic laminate more than the chip due to the differences in the CTE. As the package (laminate, solder and chip) begins to cool, the solder begins to solidify (e.g., at about 225° C.) and the laminate begins to shrink as the chip remains substantially the same size. The chip, substrate and solder joints must deform to maintain electrical and mechanical continuity during cooling which give rise to a complicated stress pattern transmitted to the chip wiring just adjacent to the solder ball. Specific sites often have been found to be more susceptible to white spots based on its location, wiring pattern or other properties. This process and resulting delamination is shown, for example, in FIG. 1.
In response to the need for lead free soldering, new techniques have been developed to bond the chip to a substrate. One such technique is Controlled Collapse Chip Connection New Process (C4NP) (also known as IMS (Injection Molded Soldering)) which is a flip chip bumping technology developed at International Business Machines Corp. IMS uses no hazardous gases or chemicals and is able to process newer lead-free solders.
IMS uses mold plates containing cavities having uniform volumes filled with solder and aligned to substrates that receive the solder from the cavities. An exemplary mold plate is shown in FIG. 2, which shows uniform cavities throughout. Cavities in the mold plates are in a pattern that is the mirror image of the solder receiving pads on the final substrate or wafer. Cavities can be produced in the mold plate by any one of a number of techniques, the selection of which is dependent upon the cavity size and pitch as well as the mold plate material. Cavity volume uniformity, however, was found to be essential to ensure quality control. Specifically, cavity uniformity was found to ensure that all sites form a complete joint and that there is no shorting between adjacent joints.
In IMS processes, a head of an IMS apparatus is filled with molten solder and moves in relation to the cavities contained in the mold plate, both of which are above solder liquidus temperature. As the head scans across the mold plate, the solder from the reservoir, under constant positive pressure, passes through a dispensing slot and into the uniform cavity volumes. After the scanning process, the mold plate is cooled to solidify the solder. After inspection of the mold plates, the mold plates may be either immediately sent for transfer or stored in a non-oxidizing environment. The mold plate is subsequently aligned to the wafer and passed through a furnace for bump transfer. Since it uses only the solder volume required for each part, there is no solder waste which is especially important for costlier alloys. Thus it is economical and environmentally friendly.